Comparison of 6522, W65C22S, R65C22 and G65SC22

1. On older versions of the 6522 and 65C22, which are not internally chip-selected, random register are read due to register select values. The W65C22S selects only register 15 ($F) internally. This feature has been added for systems which have indeterminate register select values.

2. When outputting the Shift Clock, the CB1 pin may be overdriven without affecting the shifting function. However, this is not recommended as it will result in high currents and possible damage to the part. Because some systems have been arbitrating the clock after data has been transferred, this feature was added.

3. There is a major design difference between the W65C22S and all previous versions of the 6522 and 65C22. The IRQB pin on the W65C22S is a standard totem pole output. It is no longer open drain and cannot be wire OR'ed. This change was made to improve the low power, high speed characteristics of the part.

4. WDC removed the internal pull-up resistors that were present on the NMOS R6522 and active pull-up transistors on the GTE G65SC22 and added bus holding devices on the W65C22S. The W65C22S design reduces power and speeds up the transition to a for applications that don't require pull-up resistors. Also, it should be noted that when driving Darlington transistors a current limiting resistor may be required for the W65C22S. The NMOS R6522 had built-in limiting with the pull-up resistor on PA port and smaller P channel transistors on the PB port. The GTE G65SC22 had active transistor pull-up devices on both the PA and PB ports that provided pull-up current when in the input mode. All W65C22S pins except PHI2 have bus holding devices. The original NMOS 6522, G65C22 and R65C22 did not have bus holding devices.