* VPB is Vector Pull (output) pin goes low when an interrupt vector is on the address bus.

** RDY is a bidirectional pin on the W65C02S. Early W65C02S version has a low impedance pull up resistor. The latest W65C02S6T devices (wafers manufactured at TSMC) no longer have the internal pull-up on the RDY pin (pin 2 PDIP, pin 3 PLCC, pin 41 QFP). When not driving RDY, WDC recommends having a pull up resistor (3.3K Ohm) to VDD on this pin. When driving RDY, WDC recommends have a current limiting resistor (3.3K Ohm) in series with the RDY pin.

*** MLB is Memory Lock (output) pin goes low during specific cycles of a read-modify-write instruction to indicate when memory should not be accessed.

**** BE is Bus Enable (input). When Bus Enable goes low this forces the Address Bus, Data Bus and RWB to a high impedance state.  BE should be tied directly to VDD (Pin 8).

IN SUMMARY: The W65C02S6T (40 pin PDIP) is mostly pin compatible by making the following modifications:

• 1.) Cut the trace to VPB (Pin 1). Optionally you can pull this pin up.
• 2.) BE (Pin 36) should be tied directly to VDD (Pin 8).
• 3.) Add a 3.3K Ohm pull-up resistor on RDY (Pin 2) if not being driven; Add a 3.3K Ohm series current limiting resistor to RDY (Pin 2) if being driven.
• 4.) WDC does not recommend using the SToP or WAIt instruction on the replacement designs that do not have a current limiting resistor.

SIGNAL DESCRIPTIONS:

Clock Signals (W65C02S)

All internal clock signals for the W65C02S are generated by the input clock signal Ø2 (IN/PHI2I).  WDC recommends using a clock oscillator for PHI2I. Also, PHI2I should be used for the system clock.

Clock Signals (R65C02/G65SC02)

The R65C02 requires an external Ø0 clock.  Ø0 is a TTL level input that is used to generate the internal clocks of the R65C02.  Two full level output clocks are generated by the R65C02.  The Ø2 clock is in phase with Ø0.  The  Ø1 clock output is 180° out of phase with  Ø0.  When the input clock is stopped, the CPU is in the standby mode.   For non-critical timing configurations, a simple RC or crystal network may be strapped between  Ø0 (IN) and  Ø1 (OUT).
Consult the Rockwell or GTE Datasheet/Databook for clock configuration options.

Clock Signals (R65C102)

The R65C102 internal clocks may be generated by a TTL level single phase input, and RC time base input, or a crystal time base input (÷ 4) using the XTLO and XTLI input pins.  Two full level output clocks are generated by the R65C102.  The  Ø2 clock output provides timing for external R/W operations.  Addresses are valid after the address setup time (t_ADS) referenced to the falling edge of  Ø2 (OUT).  The  Ø4 output is a quadrature output clock that is delayed from the falling edge of the  Ø2 clock by delay time t_AVS.  Using the Ø4 clock, addresses are valid at the rising edge of Ø4.
Consult the Rockwell Datasheet/Databook for clock configuration options.


Clock Signals (R65C112)

All internal clock signals for the R65C112 and W65C02S are generated by the input clock signal Ø2 (IN).  Since this device is intended to be operated in the slave mode it does not have internal clock generation, but rather requires the external clock Ø2 (IN) from a host device.
Consult the Rockwell Datasheet/Databook for clock configuration options.